The present invention relates to finite field arithmetic circuits, and more particularly to finite field multiplication and division circuits for error correction coding and decoding.
Reed-Solomon error-correcting codes help reduce bit error rate (BER) in applications such as data storage, digital video broadcasts, and wireless communications. Reed-Solomon codes operate on finite fields (GF(2m)). For high speed and low power, complex finite field arithmetic operations such as multiplication and division must be implemented efficiently.
Several different architectures that currently perform finite field arithmetic operations include standard, normal, and dual basis representations. For each representation, bit-parallel, bit-serial and digital architectures have been proposed for different application speed requirements. Most designs focus on reducing circuit area to improve speed.
Increased demand for portable DSP architectures has generated significant interest in the design of low power VLSI systems. For finite field arithmetic circuits, many approaches have been proposed for reducing power dissipation. For example, the impact of a primitive polynomial p(x) on power dissipation has been studied. The use of an XOR-tree has also been studied as a low power approach for finite field multipliers.
A method and apparatus according to the invention reduces power dissipation of a finite field arithmetic circuit having first and second circuit inputs. A first circuit transition probability of the first circuit input is calculated by applying a random input to the first circuit input and a constant input to the second circuit input. A second circuit transition probability of the second circuit input is calculated by applying a constant input to the first circuit input and a random input to the second circuit input. The first circuit transition probability is compared with the second circuit transition probability. One of the first and second circuit inputs having a lower circuit transition probability is selected.
In other features, a first time-varying rate that a first input signal to the arithmetic circuit varies is compared with a second time-varying rate that a second input signal to the arithmetic circuit varies. One of the first and second input signals having a higher time-varying rate is selected.
In yet other features, the selected one of the first and second input signals is coupled to the selected one of the first and second circuit inputs.
In other features, the circuit transition probability of the first circuit input is determined by computing node transition probabilities of circuit nodes associated with the first circuit input. The circuit transition probability of the second circuit input is determined by computing node transition probabilities of circuit nodes associated with the second circuit input.
In other features, the arithmetic circuit is a finite field multiplier. The finite field multiplier is one of a semi-systolic multiplier and a Mastrovito multiplier.
In still other features, the arithmetic circuit is a finite field multiplier implemented in a finite field divider. The finite field divider is implemented as an inverter that is connected to the finite field multiplier. The finite field multiplier is one of a semi-systolic multiplier and a Mastrovito multiplier and the inverter is implemented directly in combinatorial logic.
In still other features, the arithmetic circuit is implemented in an error correcting coding circuit. The error correction coding circuit is a Reed-Solomon error correction coding circuit.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.